1. Field of the Invention
The present invention relates to integrated circuits, and more specifically to a circuit for generating a controlled activation signal.
2. Description of Related Art
Digital integrated circuits such as microprocessors, microcontrollers, semiconductor memories, applications specific integrated circuits (ASICs), and programmable logic arrays (PLAs) are now widely used in electronic systems. After such integrated circuits are manufactured, they must be tested to insure proper operation. Because it is not practical to individually test every elementary logic circuit (e.g., transistor) in the integrated circuit for every possible situation, the testing is typically limited to the application of test vectors (or stimuli) to the inputs of the integrated circuit. For each stimulus, a comparison is made of the logic signals output by the integrated circuit and the expected output.
Generally, an external apparatus ("tester") is used to generate the input test vectors. The tester is driven by an automatic test pattern generation program that employs an automatic test pattern generation (ATPG) algorithm. For each possible defect being considered, the program determines the stimuli that will propagate the defect to the outputs of the integrated circuit. However, not all defects are capable of being detected so the exhaustivity of the testing (i.e., the ratio of the number of detectable faults to the number of possible faults) is rarely equal to 100%.
In order to increase the exhaustivity of the testing, it has been proposed to introduce into the integrated circuit access and observation devices such as shift registers. Such a shift register is formed by connecting the internal storage registers of the integrated circuit in series in a test mode. In normal mode, the storage registers fulfil their normal circuit functions. Thus, the storage registers have a twofold use: normal mode use as internal storage registers, and test mode use as part of a shift register that operates as an access and observation device for a logic unit of the integrated circuit being tested. To allow for such dual operation, the internal storage registers are both connected in series with one another and connected in parallel to the inputs or outputs of the logic unit to be tested.
FIG. 1 shows an internal storage register of an integrated circuit. A D flip-flop FF has a clock input CL that is sensitive to a signal edge (as is indicated by the "&gt;" sign). That is, the flip-flop stores the logic value present at the input D when a signal edge (e.g., a leading edge) arrives at the clock input CL, and delivers the stored logic value to the output Q when the next leading edge arrives at the clock input CL. Thus, logic values are stored in the flip-flop FF between two leading edges of the activation signal CLK. (The internal storage registers of the integrated circuit can also or alternatively be formed by devices that are sensitive to voltage levels and not signal edges, such as logic latches.)
During operation, an activation signal CLK is supplied to the clock input CL of the flip-flop. In normal mode, the activation signal is generated from a periodic clock signal H (e.g., the clock signal of the system that includes the integrated circuit) and a control signal E. More specifically, the clock signal H and the control signal E are combined in an AND operation using an AND gate 5 or a controlled switch (e.g., a MOS transistor or a tristate logic gate controlled by the control signal). The control signal E is generated from other internal signals of the integrated circuit through sequential and/or combinational logic so as to generate the activation signal CLK when necessary. When active, the control signal E allows the clock signal H to be transmitted as the activation signal CLK to the clock input CL of the flip-flop.
In test mode, the integrated circuit can be tested according to the scan test method. In the scan test method, in a loading phase, data elements are serially transmitted through the sift register to each of the flip-flops forming the shift register, and the outputs of the flip-flops are connected to inputs of the logic unit to be tested. In a capture phase, the operation under test is started and the output data elements are transmitted through the logic unit to the inputs of other flip-flops for storage. Then, in an extraction phase, the captured data elements are serially transmitted through the shift register to an output of the integrated circuit for analysis by the tester.
To use the scan test method, additional circuitry must be provided for configuring the flip-flops of the integrated circuit as part of a shift register that provides access to and observation of the logic unit to be tested. In particular, the additional circuitry allows a test mode activation signal to be provided to the clock inputs of the flip-flops of the shift register in the test mode. The test mode activation signal is generated using the periodic clock signal H described above and a test mode control signal (e.g., a control signal that is delivered from the tester to an input of the integrated circuit).